Dust Study, Transport, and Electrostatic Removal for Exploration Missions

WP2 - Development of sub-units and units

Design of the hardware sub units and units that will constitute the breadboard instrument: 

  • Front end electronics
  • HVPS unit
  • LVPS unit
  • Control and processing unit (including firmware)
  • Electrodes/probes
  • Mechanical enclosure of the instrument

Objectives

Design the HW sub units and units that will constitute the BB instrument.

Lead / Participants

TASE, BIRA-IASB, CSIC

Description

Task 2.1 Front end development (lead: BIRA-IASB)

BIRA-IASB: Based on the requirements defined in task 1.2, development of the front end electronics (from the output of the electrodes/probes to the analogue to digital converters - included). The front end for the three sensors will be based on the already developed SLP instrument that currently flies on board the PICASSO CubeSat but will require modifications to meet the new requirements.
Development of the EGSE, test and validation of the front end.

Task 2.2 HVPS development (lead: TASE)

TASE: Development of the HVPS unit for the dust collector that fulfils the requirements set in Tasks 1.2 and 1.3.
The output voltage shall be a few kV. The amplitude and polarity of the output voltage shall be controllable during operation. The HVPS will include various kinds of short-circuit protection, including an appropriate grounding scheme.
Development of the EGSE, test and validation of the HVPS.

Task 2.3 LVPS development (lead: TASE)

TASE: Development of the LVPS unit of the instrument that fulfils the requirements set in Tasks 1.2 and 1.3. The LVPS shall deliver the required voltages for all the other sub-units/units of the instrument with an appropriate grounding scheme.
Development of the EGSE, test and validation of the LVPS.

Task 2.4 Development of the control and processing unit (lead: CSIC)

CSIC: Based on the requirements defined in Tasks 1.2 and 1.3 design, manufacture and test of the digital part of the instrument, including the firmware to be programmed in the Field-Programmable Gate Array (FPGA) installed in the DPU.
TASE: To advise in the design of the DPU and cooperate in the manufacturing of the board.
Development of the EGSE, test and validation of the control and processing unit.

Task 2.5 Probes/electrodes development (lead: TASE, participants: BIRA-IASB)

TASE: Based on Particle-in-cell (PIC) simulations (e.g. SPIS), design of the dust electrodes, Langmuir probes and E-Field probes. The geometry, dimensions, coating and material will be chosen to fulfil the requirements defined in task 1.2. Manufacturing different prototypes of electrodes/probes. For each sensor (E-Field and Langmuir probes, Dust electrodes) several probe/electrode designs will be proposed and manufactured so that they can be tested and compared in relevant environment in WP4 to select the most suitable design.
BIRA-IASB: Gives support in probes/electrodes design, especially for Langmuir probes.

Task 2.6 Development of the mechanical enclosure (lead: CSIC, participants: TASE)

CSIC: Based on the requirements defined in Tasks 1.2 and 1.3, design and manufacture the mechanical enclosure of the instrument. The enclosure will be part of the EMI/EMC mitigation measures.
TASE: To advise in the design.